One of the most important factors influencing purchasing of integrated circuits is reliability. Thus manufacturers employ various tests to ensure that each IC is defect-free.
One well known and highly dependable method of testing a CMOS IC for defects is to measure the quiescent current flow in the IC resulting from the V.sub.DD power supply. This test, which is often referred to as an I.sub.DDQ test, is typically implemented by allowing an IC to reach a stable logic state and, while the IC remains in that logic state, measuring the quiescent current flow in the IC. In such a state, a defect-free CMOS IC chip should draw no DC current and should have a leakage current not exceeding approximately 10 .mu.A. On the other hand, an IC having a manufacturing defect as small as a one micron diameter "hot spot" typically exhibits I.sub.DDQ current flow on the order of several hundred micro-amps and, in some instances, may be as great as several milli-amps. As such, I.sub.DDQ testing accurately detects manufacturing faults which may be difficult to detect through performance evaluation or other functional testing techniques. It has been found that ICs screened by such I.sub.DDQ testing have as much as ten times fewer manufacturing defects than do ICs not so screened.
A conventional CMOS logic circuit has complimentary pairs of N-channel and P-channel transistors which allows such a circuit to eliminate, in its quiescent state, DC current flow. For example, an n-input CMOS NOR circuit has each of its logic inputs connected to a gate of an associated one of n N-channel pull-down transistors coupled in parallel between the logic output and ground. Each of these logic inputs is also connected to a gate of an associated one of n P-channel pull-up transistors coupled in series between the logic output and the V.sub.DD supply. Although drawing no DC current, which as will be described below is necessary for I.sub.DDQ testing, this complimentary nature undesirably slows the speed of logic operations having a large number of inputs. Where it is desired to have, for instance, 16 logic inputs, the required 16 series-connected P-channel pull-up transistors will result in a very long gate delay and, thus, undesirably reduce the speed of the circuit.
It is possible to increase the speed of such circuits having large numbers of logic inputs by replacing the plurality of series-connected P-channel pull-up transistors with a single P-channel pull-up transistor having its gate tied to ground, as illustrated in FIG. 1.
CMOS buffer circuit 10, shown as part of a CMOS OR gate 11, is configured as a sense amplifier. A plurality of input signal lines A.sub.0 -A.sub.n are coupled to input node A via N-channel MOS pull-down transistors MN.sub.0 -MN.sub.n, respectively. A P-channel MOS weak pull-up transistor MP.sub.1 is connected between the voltage supply V.sub.DD and input node A. Transistor MP.sub.1 has its gate connected to ground potential and thus remains in a conductive state. Capacitor C.sub.1 models the capacitive nature of input node A. If all input signals A.sub.0 -A.sub.n are logic low, current flow through transistor MP.sub.1 charges the capacitive load C.sub.1 toward V.sub.DD and, accordingly, pulls node A high. This logic high signal is inverted by a CMOs inverter 12 and appears as a logic low at output terminal Z. If, on the other hand, one or more of input signals A.sub.0 -A.sub.n is high, node A will be pulled low and, accordingly, a logic high signal will appear at terminal Z.
Detecting small manufacturing defects in circuit 10 using an I.sub.DDQ test may, however, be problematic. The gate of transistor MP.sub.1 is connected to ground potential and, thus, transistor MP.sub.1 remains on at all times. Accordingly, a high input signal at any one of pull-down transistors MN.sub.Al -MN.sub.An will create a DC current path from V.sub.DD to ground through pull-up transistor MP.sub.1. It follows that if, in its stable logic state, any one of input signals A.sub.0 -A.sub.n is high, circuit 10 will conduct DC current. Although this DC current may be on the order of only a few micro-amps for each such circuit 10, ICs containing thousands of such circuits 10 may exhibit a resultant DC current exceeding several Amps. Such a large DC current essentially "drowns out" and renders impossible to detect the significantly smaller current resulting from manufacturing defects and, thus, eliminates the ability to perform I.sub.DDQ testing on circuit 10. This inability, in turn, may adversely affect the reliability ratings of circuit 10.